Power estimation for a circuit design that is to be implemented in a programmable IC (integrated circuit) such as a PLD (programmable logic device) is typically performed using designer-estimated resource counts or information from a completely implemented design. The power estimation also uses a clock frequency and global toggle rate defaults, which may be individually changed by the designer.
These approaches to power estimation can have a number of disadvantages. Designer estimation of logic resources can be substantially inaccurate compared to what is actually implemented in the programmable IC by the design tools. The exact programmable logic resources called out by synthesis, technology mapping and performance optimizations are difficult for the designer to predict. Also, generic or global toggle rate defaults may be approximately accurate on averages, but are unlikely to work well on all designs and fail to account for the variability within a design for different processing structures. For example, specific structures and paths within a design have been observed to have significant variance from the design average. Further, designer estimates of toggle rates can be quite inaccurate relative to the actual toggle rates of structures in an implemented design. In addition, it is time-consuming and costly to have to complete a design such that it can be fully implemented in a target programmable IC in order to determine the power consumption.
The present invention may address one or more of the above issues.